• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A digital signal is encoded for error correction, and the encoded digital signal is transmitted in M transmitting paths. The signal to be encoded occurs as N sequences of data words. A plurality n of sequences of error correcting words are generated from respective words of the N sequences delayed by respective different delay times of (D-di) words, where di is a whole number associated with an ith one of the n error correcting word sequences. The resulting N data word sequences and n error correcting word sequences are provided with respective different total delay times, so that the total delays of the N sequences differ by an integral number D of words from one another. Blocks of the delayed N data sequences and n error correcting word sequences are formed and the blocks are cyclically distributed among the M transmitting paths. The values of M, N, n, D, and di are selected so that the least common multiple of any two values of (d-di) is greater than (N+n-1)D; and for any value of (D-di), (d-di) and M are relatively prime. Favorably, M is selected as 2 k, and (D-di) is odd.
    公开号:SU1327804A3
    申请号:SU813327708
    申请日:1981-08-13
    公开日:1987-07-30
    发明作者:Сонода Такенори；Ватанабе Нобухико；Танака Масато
    申请人:Сони Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to digital signal transmission systems and can be applied to multichannel information systems.
    The aim of the invention is to improve noise immunity.
    Figure 1 shows a diagram of the transmitting side of the device; figure 2 - diagram of the receiving side of the device; in fig. encoder scheme; figure 4 - diagram of the decoder.
    The device contains on the transmitting side (figure 1) the elements 1, - magnetic recording of signals, inputs 2 ,, and 2.J devices, encoders 3 and 3j, de-- multiplexer 4, modulators 5 ,,, amplifiers 6 6, input 7 synchronization, encoder 8, modulator 9 and amplifier 10.
    On the receiving side (FIG. 2), the device contains amplifiers, amplifier 12, clock signal, signal selectors 13, clock signal selectors 14, demodulators 15 elements 16, delays, demodulator 17, control decoder 18, multiplexer 19, decoders 20 and 20j, elements 2C - 21 magnetic signal readout.
    The encoder (FIG. 3) contains first delay elements 22 and second delay elements 23, adders 24 and 25. The decoder (FIG. 4) contains first delay elements 26, first error correction block 27, second delay elements 28, second error correction block 29 , block 30 error compensation and driver signals.
    The device works as follows.
    At the inputs of the transmitting side 1 and 2. information signals with pulse code modulation are received.
    A demultiplexer 4 is designed to distribute two signals with pulse code modulation of CH and CH j over eight tracks.
    In this case, the demultiplexer 4 generates eight separate output signals, which are fed to the corresponding modulators 5 - 5. The signals from the outputs of the modulators through the corresponding amplifiers 6, - 6f, are fed in series to the fixed elements 1 - - 1 fi.
    At the same time, a signal is sent to the input of the control signal, from where it is post-tuned to
    the input of the encoder 8. From the output of the encoder, a suitably coded y-guiding signal is fed to the mod (. torus 9, which is via UST (chl 10 is connected to the signal recording element).
    The signal is recorded in the form in which self-synchronization of the decoder is provided, and the intervals between bits in the information signals are used to control the clock frequency. Pass through selectors 13, - 13
    5, the received information signals through the demodulators 15-15 are fed to the corresponding 1e delay elements 16. Simultaneously from the output of the selector 14 of the clock signal
    0 through the demodulator 17 to the decoder 18 receives control signals. The predetermined address signals, which are contained in the signals recorded on the control track of the vehicle, are decoded in block 18. The address signals arriving at elements 16, - 16 | delays, ensure the allocation of recorded addresses in storing electrical circuits that enter
    0 to the composition of the specified electric centers. Adjust the time axis. Elements 16 - 16 of the delay from the output of the source of the reference clock signals receive the corresponding
    reading address signals.
    Eight output information signals from the corresponding elements 16 - 16 delays arrive at
    The Q inputs of the multiplexer 19, which provides the conversion of eight signals reproduced from a tape into two encoded audio signals with pulse code modulation. These
    5, two encoded signals from multiplexer 19 are transmitted to respective decoders 20 and 20, which are mutually complementary with respect to encoders 3 and 3,. Decoders
    0 20 and 20j are intended to correct errors that may occur during the execution of recording and reproducing operations, as well as to hide any errors that are not corrective. Finally, the restored audio signals with pulse-code modulation of CH and CH come to the corresponding output terminals.
    3
    Encoders 3 and 3, included in the recording system, have the same device and include a multiple delay electrical circuit, similar to that shown in FIG. 3;
     Each of the audio signals with pulse-modulated modulation of CH and CH is subdivided into six separate sequence of words, including sequences of even information words W (o) jW (2) W (4) and followers of Complexity of odd information words W (l), W (3) and W (5).
    Fig. 4 illustrates in more detail the decoders 20 and 20 included in the composition of the device shown in Fig. 2, while they have the same design and are complementary with respect to the device shown in Fig. 3. The originally reproduced words coming from the output of multiplexer 19 are processed to detect errors in the CRC cyclic overflow code control block (not shown), and the erroneous words are supplied with a pointer binary bit. After that, the block of words is divided into eight sequences, which include sequences of even words-and (O), W (2) and W (4), word sequences with information about parity and P (0) and Q ( 0), as well as sequences of odd words W (l), W (3) and W (5). These sequences arrive at a de-interlacing cascade 26, equipped with delays, which are designed to compensate for delays entered in the word-sequence by the corresponding interlacing cascade 23 included in the encoder 3 or 3. The de-interleaving cascade 26 is followed by block 27, which is designed to correct for errors in the words included in the sequences W (0), W (2), W (4), P (0), W (l), W (3) and W (5). This correction is given by ect by checking: are the words in the second sequence of words with information about the parity Q (().
    Decoded and compensated word sequences W (0) - W (5) from the output of block 27 are sent to a former in which there are six consecutive 27804. -
    information words are converted into a single digital channel, which provides the restoration of the audio signal with pulse code modulation.
    权利要求:
    Claims (3)
    [1]
    Invention Formula
    Q 1. A device for transmitting and receiving digital signals, containing on the transmitter side, information signal encoders, whose inputs are the information inputs of the device, and the outputs are connected to the inputs of the demultiplexer, the outputs of which through corresponding chains from the serially connected modulator and amplifier are connected to entrances
    2Q elements of magnetic signals recording, on the receiving side the outputs of each magnetic signal reading element are connected to the same amplifier, multiplexer, the outputs of which
    25 through appropriate decoders are connected to the outputs of the device, this is because in order to improve noise immunity, on the transmitting side, the synchronization input is connected via a serially connected encoder, modulator and amplifier connected to the video element of the magnetic recording of signals, on the receiving side syn selectors are introduced. demodulators, delay elements and a decoder of control signals, the output of each amplifier through a chain of serially connected clock selector, a demodule Q of the torus and a delay element connected to the corresponding input of the multiplexer, the output of the synchronization amplifier through a serially connected clock selector, demodulator
    45
    and a control signal decoder is connected to the control inputs of the delay elements.
    [2]
    2. The device according to claim 1, about aphid - Q, since each encoder is made on adders and delay elements, the inputs of the encoder are connected to the corresponding inputs of the first adder, the outputs of which through the first delay elements are connected to the inputs of the second adder, the outputs of which through the second delay elements are connected to the outputs of the encoder.
    [3]
    3. The device according to claim 1, characterized in that the decoder is made on delay elements, error correction blocks, error compensation blocks and a signal conditioner, the decoder inputs are connected to the inputs of the corresponding delay elements, the outputs of which are connected to the inputs
    the first error correction block, the outputs of which are connected to the second delay elements, the outputs of which are connected to the second error correction block, the outputs of which through the error compensation block are connected to the signal conditioner whose output is the decoder output.
    f / 8. J
    Editor Y. Sereda
    Compiled by E.Bakeev
    Tehred L. Serd (bent corrector V. Hearn to
    Order 3396/59 Circulation 543Subscription
    VNISh State Committee of the USSR
    for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5
    Production and printing company, Uzhgorod, Projecto st., 4
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    引用文献:
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    法律状态:
    优先权:
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    JP55112014A|JPH0157427B2|1980-08-14|1980-08-14|
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